Renesas H8S/2368 Series Hardware Manual page 42

Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 442
Figure 10.40 TCIV Interrupt Setting Timing .............................................................................. 442
Figure 10.41 TCIU Interrupt Setting Timing .............................................................................. 443
Figure 10.42 Timing for Status Flag Clearing by CPU............................................................... 443
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation................................ 444
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode................. 445
Figure 10.45 Contention between TCNT Write and Clear Operations ....................................... 446
Figure 10.46 Contention between TCNT Write and Increment Operations................................ 446
Figure 10.47 Contention between TGR Write and Compare Match ........................................... 447
Figure 10.48 Contention between Buffer Register Write and Compare Match .......................... 448
Figure 10.49 Contention between TGR Read and Input Capture................................................ 448
Figure 10.50 Contention between TGR Write and Input Capture............................................... 449
Figure 10.51 Contention between Buffer Register Write and Input Capture .............................. 450
Figure 10.52 Contention between Overflow and Counter Clearing ............................................ 450
Figure 10.53 Contention between TCNT Write and Overflow ................................................... 451
Section 11 Programmable Pulse Generator (PPG)
Figure 11.1 Block Diagram of PPG .......................................................................................... 454
Figure 11.2 Overview Diagram of PPG .................................................................................... 463
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)................................ 464
Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ........................................... 465
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) ................................... 466
Figure 11.6 Non-Overlapping Pulse Output.............................................................................. 467
Figure 11.7 Non-Overlapping Operation and NDR Write Timing............................................ 468
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example) ........................... 469
Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) .............. 470
Figure 11.10 Inverted Pulse Output (Example)........................................................................... 471
Figure 11.11 Pulse Output Triggered by Input Capture (Example) ............................................ 472
Section 12 8-Bit Timers (TMR)
Figure 12.1 Block Diagram of 8-Bit Timer Module ................................................................. 474
Figure 12.2 Example of Pulse Output ....................................................................................... 482
Figure 12.3 Count Timing for Internal Clock Input .................................................................. 482
Figure 12.4 Count Timing for External Clock Input................................................................. 483
Figure 12.5 Timing of CMF Setting.......................................................................................... 483
Figure 12.6 Timing of Timer Output......................................................................................... 484
Figure 12.7 Timing of Compare Match Clear ........................................................................... 484
Figure 12.8 Timing of Clearance by External Reset ................................................................. 485
Figure 12.9 Timing of OVF Setting .......................................................................................... 485
Figure 12.10 Contention between TCNT Write and Clear.......................................................... 488
Figure 12.11 Contention between TCNT Write and Increment .................................................. 489
Figure 12.12 Contention between TCOR Write and Compare Match ........................................ 490
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of WDT ........................................................................................ 496
Figure 13.2 Operation in Watchdog Timer Mode ..................................................................... 501
Rev. 2.00, 05/03, page xlii of lii