Renesas H8S/2368 Series Hardware Manual page 11

Item
5.4.1 External Interrupts
6.8.1 Operation
Section 9 I/O Ports
Table 9.1 Port Functions
9.1.4 Pin Functions
• P13/PO11*
1
/TIOCD0/TCL
1
KB/TEND1*
• P12/PO10*
1
/TIOCC0/TCL
1
KA/TEND0*
• P11/PO9*
1
/TIOCB0/
1
DREQ1*
9.2.4 Pin Functions
• P24/PO4*
1
/TIOCA4/
RxD4/TMO0
9.3.5 Port Function Control
Register 2 (PFCR2)
9.3.6 Pin Functions
• P35/SCK1/SCL0/(OE)*
Page Revision (See Manual for Details)
90 Description amended in the 13th line.
Using ISCRL, it is possible to select whether an
interrupt is generated by a low level, falling edge,
rising edge, or both edges, at pins IRQ7 to IRQ0.
187 Description added in the 1st line.
Table 6.7 shows whether an idle cycle is inserted or
not in mixed access to normal space and DRAM.
300 Description of port 2 amended.
(Error) General I/O port also functioning as PPG
outputs, TPU I/Os, TMR I/Os, and bus control I/Os →
(Correction) General I/O port also functioning as PPG
outputs, TPU I/Os, and TMR I/Os
309 Description amended in the 5th line.
(Error) bit TEEI → (Correction) bit TEE1
310 Description amended in the 5th line.
(Error) bit TEEO → (Correction) bit TEE0
311 Description amended in the 3rd line.
...(by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0
in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0),...
318 Description amended in the 3rd line.
The pin function is switched as shown below
according to the combination of the TPU channel 4
settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to
IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in
TCR4), bit NDER4*
P24DDR, and bit OS3 to OS0 in TCSRO of TMR.
Table amended.
RE
TPU channel 4
settings
OS3 to OS0
P24DDR
NDER4
Pin function
326 Note added.
Note: * In the H8S/2366, this bit is reserved. This bit
327 Amended.
(Error) C/A → (Correction) C/A
3
1
in NDERL, bit RE in SCI_4, bit
0
(1) in table below
All 0
— 0
— —
TIOCA4 output P24 P24
input output
is always read as 1 and the write value should
always be 1.
Rev. 2.00, 05/03, page xi of lii
1
(2) in table below —
Not all 0 —
1 1 — —
0 1 — —
PO4 TMO0 RXD4 input
1
output* output
2
TIOCA4 input*