Figure 24.10 Basic Bus Timing: Three-State Access (Cs Assertion Period Extended) - Renesas H8S/2368 Series Hardware Manual

A23 to A0
to
Read
(RDNn = 1)
D15 to D0
Read
(RDNn = 0)
D15 to D0
,
Write
D15 to D0
,
Figure 24.10 Basic Bus Timing: Three-State Access (CS
T
h
t
AD
t
CSD1
t
AS1
t
ASD
t
AS3
t
AS3
t
AS4
t
WDS3
t
WDD
t
DACD1
T T
1 2
t
t
RSD1 RSD1
t
AC6
t
RSD1
t
AC4
t
WRD2
t
WRD1
t
WSW2
CS Assertion Period Extended) CS CS
Rev. 2.00, 05/03, page 749 of 820
T T
3 t
t
t
AH1
ASD
t
AH3
t t
RDS1 RDH1
t
t AH2
RSD2
t t
RDS2 RDH2
t
AH3
t
WDH3
t
DACD2