Figure 10.39 Tgi Interrupt Timing (Input Capture); Figure 10.40 Tciv Interrupt Setting Timing - Renesas H8S/2368 Series Hardware Manual

16-bit single-chip microcomputer
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φ
Input capture
signal
TCNT
TGR
TGF flag
TGI interrupt
TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing.
Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
Rev. 2.00, 05/03, page 442 of 820
N

Figure 10.39 TGI Interrupt Timing (Input Capture)

H'FFFF

Figure 10.40 TCIV Interrupt Setting Timing

N
H'0000

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