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9.6.4 Pin Functions
• P81/TxD3
9.8.6 Port Function Control
Register 0 (PFCR0)
9.14.4 Pin Functions
• PG3/CS3/RAS3*,
PG2/CS2/RAS2*
14.3.9 Bit Rate Register
(BRR)
Table 14.3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
Table 14.4 Maximum Bit
Rate for Each Frequency
(Asynchronous Mode)
Table 14.5 Maximum Bit
Rate with External Clock
Input (Asynchronous Mode)
Table 14.6 BRR Settings
for Various Bit Rates
(Clocked Synchronous
Mode)
Table 14.7 Maximum Bit
Rate with External Clock
Input (Clocked Synchronous
Mode)
Table 14.8 Examples of Bit
Rate for Various BRR
Settings (Smart Card
Interface Mode) (when n = 0
and S = 372)
Rev. 2.00, 05/03, page xii of lii
Page
Revision (See Manual for Details)
338
Amended.
(Error) TxD3 input → (Correction) TxD3 output
344
Bit table amended.
Bit
Bit Name
7
CS7E
6
CS6E
5
CS5E
4
CS4E
3
CS3E
2
CS2E
1
CS1E
0
CS0E
372
Table amended.
Operating
mode
EXPE
CSnE
0
RMTS2*
—
to
RMTS0*
PGnDDR
0
Pin
PGn
function
input
Values when operating frequency φ is 2 MHz to
529
7.3728 MHz deleted.
Values when operating frequency φ is 2 MHz to
531
7.3728 MHz deleted.
Values when operating frequency φ is 2 MHz to
532
7.3728 MHz deleted.
Values when operating frequency φ is 2 MHz and
533
4 MHz deleted.
Values when operating frequency φ is 2 MHz, 4 MHz,
534
and 6 MHz deleted.
Values when operating frequency φ is 7.1424 MHz
535
deleted.
Initial Value
R/W
Description
1
R/W
to
Enable/disable corresponding
1
R/W
0: Set as I/O port.
1
R/W
1: Set as
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1, 2, 4
—
0
1
—
Area n is in
Area n is in
—
normal space
DRAM*
space
1
0
1
—
0
PGn
PGn
PGn
*
output
input
output
output
input
enable
output.
output pin.
(n = 7 to 0)
7
1
0
1
—
Area n is in
Area n is in
normal space
DRAM*
space
1
0
1
0
1
—
PGn
PGn
PGn
PGn
output
input
output
input
output
output
*
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