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1.3
Pin Description
1.3.1
Pin Arrangement
Figures 1.3 to 1.6 show the pin arrangements of this LSI.
91
PG2/
/
92
PG3/
/
93
AV
CC
94
Vref
95
P40/AN0/(
)
96
P41/AN1/(
)
97
P42/AN2/(
)
98
P43/AN3/(
)
99
P44/AN4/(
)
100
P45/AN5/(
)
101
P46/AN6/(
)
102
P47/AN7/(
)
103
P94/AN12/DA2
104
P95/AN13/DA3
105
AV
SS
106
PG4/
/
107
PG5/
108
PG6/
109
P50/TxD2/
110
P51/RxD2/
111
P52/SCK2/
112
P53/
/
113
P35/SCK1/SCL0/(
)
114
P34/SCK0/SCK4/SDA0
115
P33/RxD1/SCL1
116
P32/RxD0/IrRxD/SDA1
117
P31/TxD1
118
P30/TxD0/IrTxD
119
MD0
120
MD1
Note: * This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version,
the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and
Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363
TFP-120
(Top view)
V
60
CC
PE7/D7
59
V
58
SS
PE6/D6
57
PE5/D5
56
PE4/D4
55
PE3/D3
54
PE2/D2
53
PE1/D1
52
PE0/D0
51
P85/SCK3
50
P27/PO7/TIOCB5
49
P26/PO6/TIOCA5
48
P25/PO5/TIOCB4/TMO1
47
P24/PO4/TIOCA4/TMO0/RxD4
46
P23/PO3/TIOCD3/TMCI1/TxD4
45
P22/PO2/TIOCC3/TMCI0
44
P21/PO1/TIOCB3/TMRI1
43
P20/PO0/TIOCA3/TMRI0
42
P17/PO15/TIOCB2/TCLKD
41
P16/PO14/TIOCA2
40
P15/PO13/TIOCB1/TCLKC/
39
P14/PO12/TIOCA1/
38
P13/PO11/TIOCD0/TCLKB/
37
P12/PO10/TIOCC0/TCLKA/
36
P11/PO9/TIOCB0/
35
P10/PO8/TIOCA0/
34
V
33
CC
NMI
32
31
function only for the on-chip emulator.
Rev. 2.00, 05/03, page 5 of 820
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