Dram Access Control Register (Draccr) - Renesas H8S/2368 Series Hardware Manual

6.3.9

DRAM Access Control Register (DRACCR)

DRACCR is used to set the DRAM interface bus specifications.
Note: The DRAM interface is not supported by the H8S/2366.
Bit Bit Name
7 DRMI
−
6
5 TPC1
4 TPC0
3 and —
2
1 RCD1
0 RCD0
Rev. 2.00, 05/03, page 128 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a DRAM
access cycle when a continuous normal space
access cycle follows a DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1-state RAS precharge cycle
01: 2-state RAS precharge cycle
10: 3-state RAS precharge cycle
11: 4-state RAS precharge cycle
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted