Operation Timing; Tcnt Incrementation Timing; Figure 12.2 Example Of Pulse Output; Figure 12.3 Count Timing For Internal Clock Input - Renesas H8S/2368 Series Hardware Manual

H'FF
TCORA
TCORB
H'00
TMO
12.5

Operation Timing

12.5.1

TCNT Incrementation Timing

Figure 12.3 shows the count timing for internal clock input. Figure 12.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
Rev. 2.00, 05/03, page 482 of 820
TCNT

Figure 12.2 Example of Pulse Output

N–1

Figure 12.3 Count Timing for Internal Clock Input

Counter clear
N N+1