Renesas H8S/2368 Series Hardware Manual page 34

17.5.1 Setting for Module Stop Mode ............................................................................ 642
17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 642
Section 18 RAM ................................................................................................643
Section 19 Flash Memory (F-ZTAT Version)...................................................645
19.1 Features............................................................................................................................. 645
19.2 Mode Transitions .............................................................................................................. 646
19.3 Block Configuration ......................................................................................................... 650
19.4 Input/Output Pins .............................................................................................................. 652
19.5 Register Descriptions ........................................................................................................ 652
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 652
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 654
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 654
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 655
19.5.5 RAM Emulation Register (RAMER)................................................................... 656
19.6 On-Board Programming Modes........................................................................................ 657
19.6.1 Boot Mode ........................................................................................................... 658
19.6.2 User Program Mode............................................................................................. 661
19.7 Flash Memory Emulation in RAM ................................................................................... 662
19.8 Flash Memory Programming/Erasing ............................................................................... 664
19.8.1 Program/Program-Verify ..................................................................................... 664
19.8.2 Erase/Erase-Verify............................................................................................... 666
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 666
19.9 Program/Erase Protection ................................................................................................. 668
19.9.1 Hardware Protection ............................................................................................ 668
19.9.2 Software Protection.............................................................................................. 668
19.9.3 Error Protection ................................................................................................... 668
19.10 Programmer Mode ............................................................................................................ 669
19.11 Power-Down States for Flash Memory............................................................................. 669
19.12 Usage Notes ...................................................................................................................... 669
Section 20 Mask ROM ......................................................................................673
Section 21 Clock Pulse Generator .....................................................................675
21.1 Register Descriptions ........................................................................................................ 675
21.1.1 System Clock Control Register (SCKCR) ........................................................... 675
21.1.2 PLL Control Register (PLLCR)........................................................................... 677
21.2 Oscillator........................................................................................................................... 678
21.2.1 Connecting a Crystal Oscillator ........................................................................... 678
21.2.2 External Clock Input............................................................................................ 679
21.3 PLL Circuit ....................................................................................................................... 680
21.4 Frequency Divider ............................................................................................................ 681
Rev. 2.00, 05/03, page xxxiv of lii