Renesas H8S/2368 Series Hardware Manual page 728

Bit Bit Name Initial Value
7 PSTOP 0
6 — 0
5 — 0
4 — 0
3 STCS 0
Rev. 2.00, 05/03, page 676 of 820
R/W Description
φ Clock Output Disable
R/W
Controls φ output.
Normal Operation
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0: φ output
1: Fixed high
R/W Reserved
Though this bit can be read from or written to, the write
value should always be 0.
— Reserved
—
These bits are always read as 0 and cannot be
modified.
R/W Frequency Multiplication Factor Switching Mode Select
Selects the operation when the PLL circuit frequency
multiplication factor is changed.
0: Specified multiplication factor is valid after transition
to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 and STC0 bits are rewritten