Register
Name
Reset
P1DR
Initialized
P2DR
Initialized
P3DR
Initialized
P5DR
Initialized
P8DR
Initialized
PADR
Initialized
PBDR
Initialized
PCDR
Initialized
PDDR
Initialized
PEDR
Initialized
PFDR
Initialized
PGDR
Initialized
SMR_0
Initialized
BRR_0
Initialized
SCR_0
Initialized
TDR_0
Initialized
SSR_0
Initialized
RDR_0
Initialized
SCMR_0
Initialized
SMR_1
Initialized
BRR_1
Initialized
SCR_1
Initialized
TDR_1
Initialized
SSR_1
Initialized
RDR_1
Initialized
SCMR_1
Initialized
SMR_2
Initialized
BRR_2
Initialized
SCR_2
Initialized
TDR_2
Initialized
SSR_2
Initialized
RDR_2
Initialized
SCMR_2
Initialized
High-
Clock
Speed
Division Sleep
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Module
All Module
Software
Stop
Clock Stop
Standby
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Initialized Initialized
Initialized Initialized
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Initialized Initialized
Initialized Initialized
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Initialized Initialized
Initialized Initialized
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Initialized Initialized
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Initialized Initialized
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Rev. 2.00, 05/03, page 729 of 820
Hardware
Standby
Module
Initialized
PORT
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
SCI_0
Initialized
Initialized
Initialized
Initialized
SCI_1
Initialized
Initialized
Initialized
Initialized
SCI_2
Initialized
Initialized
Initialized