Figure 6.51 Example Of Idle Cycle Operation After Dram Access (Consecutive Reads In Different Areas) (Idlc = 0, Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.51 and 6.52 show examples of
idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if
bits ICIS1 and ICIS0 are set to 1.
Note: The DRAM interface is not supported by the H8S/2366.
DRAM space read External address space read DRAM space read
T T T T T T T T T T T
p r c1 c2 i 1 2 3 i c1 c2
Address bus
,
Data bus
Idle cycle
Figure 6.51 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
Rev. 2.00, 05/03, page 184 of 820