Sequential Mode; Table 7.5 Register Functions In Sequential Mode - Renesas H8S/2368 Series Hardware Manual

7.5.2

Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5 Register Functions in Sequential Mode
Register
23
MAR
23 15
H'FF
IOAR
15
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7.3 illustrates operation in sequential mode.
Rev. 2.00, 05/03, page 230 of 820
Function
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source Destination
address address
register register
0
Destination Source
address address
register register
0
Transfer counter
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Incremented/
decremented every
transfer
Fixed
transfer; transfer
ends when count
reaches H'0000