Register Descriptions; Figure 8.1 Block Diagram Of Dtc - Renesas H8S/2368 Series Hardware Manual

Interrupt controller
Interrupt
request
CPU interrupt
request
Legend
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERG
DTVECR
8.2

Register Descriptions

DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a
set of register information that is stored in an on-chip RAM to the corresponding DTC registers
and transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to G (DTCERA to DTCERG)
• DTC vector register (DTVECR)
Rev. 2.00, 05/03, page 276 of 820
DTC
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to G
: DTC vector register

Figure 8.1 Block Diagram of DTC

Internal address bus
Internal data bus
On-chip
RAM