Figure 7.23 Example Of Dreq Pin Falling Edge Activated Block Transfer Mode Transfer - Renesas H8S/2368 Series Hardware Manual

Bus release
Address
bus
DMA
Idle
control
Channel
Request
Minimum
of 2 cycles
[1] [2]
[1] Acceptance after transfer enabling; the
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle;
[4] [7] When the
is completed.
(As in [1], the
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1 DREQ
DREQ DREQ
for the channel for which the DREQ pin is selected.
Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
1 block transfer
DMA DMA
read write
Transfer source Transfer destination
Read Write
Request clear period
[3]
Acceptance resumes
pin high level sampling on the rising edge of
pin high level has been sampled, acceptance is resumed after the dead cycle
pin low level is sampled on the rising edge of , and the request is held.)
DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ DREQ
DMA Bus DMA
dead release read
Transfer source
Dead Idle Read
Request clear period
Request
Minimum
of 2 cycles
[4] [5] [6]
pin low level is sampled on the rising edge of ,
Rev. 2.00, 05/03, page 255 of 820
1 block transfer
DMA DMA
write dead
Transfer destination
Write Dead
Acceptance resumes
starts.
Bus
release
Idle
[7]