Figure 15.1 Block Diagram Of I - Renesas H8S/2368 Series Hardware Manual

Output
SCL
control
Noise canceler
Output
SDA
control
Noise canceler
Legend:
ICCRA
ICCRB
ICMR
ICSR
ICIER
ICDRT
ICDRR
ICDRS
SAR
Rev. 2.00, 05/03, page 590 of 820
Transmission/
control circuit
Bus state
decision circuit
Arbitration
decision circuit
2
: I C bus control register A
2
: I C bus control register B
2
: I C mode register
2
I C status register
:
2
I C interrupt permission register
:
2
I C transmission data register
:
2
I C reception data register
:
2
I C bus shift register
:
Slave address register
:

Figure 15.1 Block Diagram of I

reception
ICDRT
ICDRS
ICDRR
ICEIR
2
C Bus Interface2
Transfer clock
generation
circuit
ICCRA
ICCRB
ICMR
SAR
Address
comparator
ICSR
Interrupt
Interrupt request
generator