Table 10.12 Tiorh_0 - Renesas H8S/2368 Series Hardware Manual

Table 10.12 TIORH_0

Bit 7 Bit 6 Bit 5
IOB3 IOB2 IOB1
0 0 0
1
1 0
1
1 0 0
1
1 x
Legend: x: Don't care
Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev. 2.00, 05/03, page 388 of 820
Description
Bit 4 TGRB_0
IOB0 Function
0 Output
1 compare
register
0
1
0
1
0
1
0 Input
capture
register
1
x
x
TIOCB0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCB0 pin
Input capture at rising edge
Capture input source is TIOCB0 pin
Input capture at falling edge
Capture input source is TIOCB0 pin
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*