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16.3
Register Descriptions
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D data register E (ADDRE)
• A/D data register F (ADDRF)
• A/D data register G (ADDRG)
• A/D data register H (ADDRH)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
16.3.1
A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 16.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width. The data can be read
directly from the CPU.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Rev. 2.00, 05/03, page 622 of 820
Channel Set 1 (CH3 = 1)
AN12
AN13
A/D Data Register which Stores
Conversion Result
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
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