Renesas H8S/2368 Series Hardware Manual page 31

Section 13 Watchdog Timer ............................................................................. 495
13.1 Features ............................................................................................................................. 495
13.2 Input/Output Pin................................................................................................................ 496
13.3 Register Descriptions ........................................................................................................ 497
13.3.1 Timer Counter (TCNT)........................................................................................ 497
13.3.2 Timer Control/Status Register (TCSR) ................................................................ 497
13.3.3 Reset Control/Status Register (RSTCSR) ............................................................ 499
13.4 Operation .......................................................................................................................... 500
13.4.1 Watchdog Timer Mode ........................................................................................ 500
13.4.2 Interval Timer Mode ............................................................................................ 501
13.5 Interrupts ........................................................................................................................... 502
13.6 Usage Notes ...................................................................................................................... 502
13.6.1 Notes on Register Access..................................................................................... 502
13.6.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 503
13.6.3 Changing Value of CKS2 to CKS0...................................................................... 504
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 504
13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 504
13.6.6 System Reset by WDTOVF Signal...................................................................... 505
Section 14 Serial Communication Interface (SCI, IrDA) ................................. 507
14.1 Features ............................................................................................................................. 507
14.2 Input/Output Pins .............................................................................................................. 509
14.3 Register Descriptions ........................................................................................................ 510
14.3.1 Receive Shift Register (RSR) .............................................................................. 511
14.3.2 Receive Data Register (RDR) .............................................................................. 511
14.3.3 Transmit Data Register (TDR)............................................................................. 511
14.3.4 Transmit Shift Register (TSR) ............................................................................. 512
14.3.5 Serial Mode Register (SMR)................................................................................ 512
14.3.6 Serial Control Register (SCR).............................................................................. 516
14.3.7 Serial Status Register (SSR) ................................................................................ 520
14.3.8 Smart Card Mode Register (SCMR) .................................................................... 527
14.3.9 Bit Rate Register (BRR) ...................................................................................... 528
14.3.10 IrDA Control Register (IrCR) .............................................................................. 537
14.3.11 Serial Extension Mode Register (SEMR) ............................................................ 538
14.4 Operation in Asynchronous Mode .................................................................................... 540
14.4.1 Data Transfer Format........................................................................................... 540
14.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ........................................................................................ 542
14.4.3 Clock.................................................................................................................... 543
14.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 544
14.4.5 Data Transmission (Asynchronous Mode)........................................................... 545
14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 547
14.5 Multiprocessor Communication Function......................................................................... 551
Rev. 2.00, 05/03, page xxxi of lii