Figure 6.1 Block Diagram Of Bus Controller - Renesas H8S/2368 Series Hardware Manual

A block diagram of the bus controller is shown in figure 6.1.
Internal bus master bus request signal
Internal bus master bus acknowledge signal
Internal bus control signals
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Legend
ABWCR : Bus width control register
ASTCR : Access state control register
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL : Wait control registers AH, AL, BH, and BL
RDNCR : Read strobe timing control register
CSACRH and CSACRL :
BROMCRH : Area 0 burst ROM interface control register
Note: * Not supported by the H8S/2366.
Rev. 2.00, 05/03, page 108 of 820
Internal address bus
CPU bus request signal
DTC bus request signal
*
*
Internal data bus
assertion period control registers H and L

Figure 6.1 Block Diagram of Bus Controller

Area decoder
External bus controller
External bus
arbiter
Internal bus controller
Internal bus
arbiter
Control registers
ABWCR ASTCR
WTCRAH WTCRAL
WTCRBH WTCRBL
RDNCR
CSACRH CSACRL
BROMCRH BROMCRL
BCR
BROMCRL : Area 1 burst ROM interface control register
BCR : Bus control register
DRAMCR* : DRAM control register
DRACCR* : DRAM access control register
REFCR* : Refresh control register
RTCNT* : Refresh timer counter
RTCOR* : Refresh time constant register
to
External bus
control signals
DRAMCR
DRACCR
REFCR
RTCNT RTCOR