Bit
Bit
Name
10
ICIS0
9
WDBE
8
WAITE
−
7 to 3
2
ICIS2
−
1 and 0
Rev. 2.00, 05/03, page 122 of 820
Initial Value
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Idle Cycle Insert 0
When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
Write Data Buffer Enable
The write data buffer function can be used for
an external write cycle or DMAC single address
transfer cycle.
0: Write data buffer function not used
1: Write data buffer function used
WAIT Pin Enable
Selects enabling or disabling of wait input by the
WAIT pin.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
Idle Cycle Insert 2
When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
Though these bits can be read from or written
to, the write value should always be 0.