Bus Release; Operation; Figure 6.55 Example Of Timing When Write Data Buffer Function Is Used - Renesas H8S/2368 Series Hardware Manual

Internal address bus
Internal read signal
External space
write

Figure 6.55 Example of Timing when Write Data Buffer Function is Used

6.10

Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access. If any of the following requests are issued in the external bus released state, the BREQO
signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
6.10.1

Operation

In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
Rev. 2.00, 05/03, page 190 of 820
T
1
A23 to A0
,
D15 to D0
On-chip memory read Internal I/O register read
External write cycle
T T
2 W
Internal memory Internal I/O register address
External address
T T
W 3