Port A Data Register (Padr); Port A Register (Porta) - Renesas H8S/2368 Series Hardware Manual

9.8.2

Port A Data Register (PADR)

PADR stores output data for the port A pins.
Bit Bit Name Initial Value
7 PA7DR 0
6 PA6DR 0
5 PA5DR 0
4 PA4DR 0
3 PA3DR 0
2 PA2DR 0
1 PA1DR 0
0 PA0DR 0
9.8.3

Port A Register (PORTA)

PORTA shows port A pin states.
PORTA cannot be modified.
Bit Bit Name Initial Value
7 PA7
—*
6 PA6
—*
5 PA5
—*
4 PA4
—*
3 PA3
—*
2 PA2
—*
1 PA1
—*
0 PA0
—*
Note: * Determined by the states of pins PA7 to PA0.
Rev. 2.00, 05/03, page 342 of 820
R/W Description
R/W Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Description
R If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
R
is performed while PADDR bits are cleared to 0, the
R
pin states are read.
R
R
R
R
R