Table of Contents
Advertisement
2
15.3.8 I
C Bus Receive Data Register (ICDRR) ............................................................. 601
2
15.3.9 I
C Bus Shift Register (ICDRS) ........................................................................... 601
15.4 Operation .......................................................................................................................... 602
2
15.4.1 I
C Bus Format..................................................................................................... 602
15.4.2 Master Transmit Operation .................................................................................. 603
15.4.3 Master Receive Operation.................................................................................... 605
15.4.4 Slave Transmit Operation .................................................................................... 607
15.4.5 Slave Receive Operation...................................................................................... 609
15.4.6 Noise Canceler ..................................................................................................... 611
15.4.7 Example of Use.................................................................................................... 611
15.5 Interrupt Request............................................................................................................... 616
15.6 Bit Synchronous Circuit.................................................................................................... 616
Section 16 A/D Converter................................................................................. 619
16.1 Features ............................................................................................................................. 619
16.2 Input/Output Pins .............................................................................................................. 621
16.3 Register Descriptions ........................................................................................................ 622
16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 622
16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 623
16.3.3 A/D Control Register (ADCR) ............................................................................ 625
16.4 Operation .......................................................................................................................... 626
16.4.1 Single Mode......................................................................................................... 626
16.4.2 Scan Mode ........................................................................................................... 626
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 627
16.4.4 External Trigger Input Timing............................................................................. 629
16.5 Interrupts ........................................................................................................................... 629
16.6 A/D Conversion Precision Definitions.............................................................................. 630
16.7 Usage Notes ...................................................................................................................... 632
16.7.1 Module Stop Mode Setting .................................................................................. 632
16.7.2 Permissible Signal Source Impedance ................................................................. 632
16.7.3 Influences on Absolute Precision......................................................................... 633
16.7.4 Setting Range of Analog Power Supply and Other Pins ...................................... 633
16.7.5 Notes on Board Design ........................................................................................ 633
16.7.6 Notes on Noise Countermeasures ........................................................................ 634
Section 17 D/A Converter................................................................................. 637
17.1 Features ............................................................................................................................. 637
17.2 Input/Output Pins .............................................................................................................. 639
17.3 Register Descriptions ........................................................................................................ 639
17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................ 639
17.3.2 D/A Control Register 23 (DACR23).................................................................... 639
17.4 Operation .......................................................................................................................... 641
17.5 Usage Notes ...................................................................................................................... 642
Rev. 2.00, 05/03, page xxxiii of lii
Advertisement
Table of Contents
