Figure 24.17 Dram Access Timing: Three-State Burst Access - Renesas H8S/2368 Series Hardware Manual

A23 to A0
,
,
Read
D15 to D0
,
Write
D15 to D0
,
Notes:
timing: when DDS = 1
timing: when RAST = 1

Figure 24.17 DRAM Access Timing: Three-State Burst Access

Rev. 2.00, 05/03, page 756 of 820
T T T
p r c1
T T T
c2 c3 c1
t
RCH
t
RCS2
T T
c2 c3
t
CPW2
t
AC8