Figure 22.1 Mode Transitions - Renesas H8S/2368 Series Hardware Manual

*1 The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
*2 Not supported by the H8S/2366.
*3 TDR, SSR, and RDR are halted (reset) and other registers are halted (retained).
*4 BC2 to BC0 are halted (reset) and other registers are halted (retained).
Reset state
High-speel mode
(Internal clock is PLL
circuit output clock)
SCK2 to
SCK0 = 0
Clock division
mode
Program execution state
: Transition after exception handling
Notes: *1 NMI, to
(8-bit timer interrupts are valid when MSTP0 = 0.)
*2 NMI, to
(IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.)
• When a transition is made between modes by means of an interrupt, the transition cannot be
made on interrupt source generation alone. Ensure that interrupt handling is performed after
accepting the interrupt request.
• From any state, a transition to hardware standby mode occurs when
• From any state except hardware standby mode, a transition to the reset state occurs when
is driven low.
pin = high
pin = low
pin = high
SLEEP
instruction
Any interrupt
SLEEP
instruction
SCK2 to
SCK0 ≠ 0
Interrupt
SLEEP
instruction
External
interrupt
, 8-bit timer interrupts, watchdog timer interrupts.

Figure 22.1 Mode Transitions

pin = low
Hardware
standby mode
SSBY = 0
Sleep mode
MSTPCR =
H'FFFF (H'FFFE),
EXMSTPCR = H'FFFF,
SSBY = 0
All
module-clocks-stop
*1
mode
SSBY = 1
Software
standby mode
*2
Program-halted state
: Power- down mode
is driven low.
Rev. 2.00, 05/03, page 685 of 820