Renesas H8S/2368 Series Hardware Manual page 47

Section 1 Overview
Table 1.1 Pin Arrangement in Each Operating Mode................................................................9
Table 1.2 Pin Functions ...........................................................................................................14
Section 2 CPU
Table 2.1 Instruction Classification .........................................................................................37
Table 2.2 Operation Notation...................................................................................................38
Table 2.3 Data Transfer Instructions........................................................................................39
Table 2.4 Arithmetic Operations Instructions ..........................................................................40
Table 2.5 Logic Operations Instructions..................................................................................42
Table 2.6 Shift Instructions......................................................................................................42
Table 2.7 Bit Manipulation Instructions ..................................................................................43
Table 2.8 Branch Instructions ..................................................................................................45
Table 2.9 System Control Instructions.....................................................................................46
Table 2.10 Block Data Transfer Instructions .............................................................................47
Table 2.11 Addressing Modes ...................................................................................................48
Table 2.12 Absolute Address Access Ranges ............................................................................50
Table 2.13 Effective Address Calculation .................................................................................52
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection .............................................................................57
Table 3.2 Pin Functions in Each Operating Mode ...................................................................61
Section 4 Exception Handling
Table 4.1 Exception Types and Priority...................................................................................69
Table 4.2 Exception Handling Vector Table............................................................................70
Table 4.3 Status of CCR and EXR after Trace Exception Handling........................................74
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling.......................75
Section 5 Interrupt Controller
Table 5.1 Pin Configuration..................................................................................................... 81
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities..................................93
Table 5.3 Interrupt Control Modes ..........................................................................................97
Table 5.4 Interrupt Response Times ......................................................................................102
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses ....................102
Section 6 Bus Controller (BSC)
Table 6.1 Pin Configuration...................................................................................................109
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................135
Table 6.3 Data Buses Used and Valid Strobes.......................................................................139
Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space ............152
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing....153
Table 6.6 DRAM Interface Pins ............................................................................................154
Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM ...............................187
Table 6.8 Pin States in Idle Cycle ..........................................................................................189
Tables
Rev. 2.00, 05/03, page xlvii of lii