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•
PG4/CS4/BREQO
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, bit BREQO, bit CS4E and bit PG4DDR.
•
PG3/CS3/RAS3*, PG2/CS2/RAS2*
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, bit CSnE, and bits RMTS2 to RMTS0*.
Operating
mode
EXPE
CSnE
0
RMTS2*
—
to
RMTS0*
PGnDDR
0
1
Pin
PGn
PGn
function
input
output
Note: * Not supported by the H8S/2366.
•
PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, and bit CsnE.
Operating
mode
EXPE
CSnE
0
PGnDDR
0
Pin function
PGn
input
Rev. 2.00, 05/03, page 372 of 820
1, 2, 4
—
1
Area n is in
Area n is in
normal space
DRAM*
space
0
1
—
CSn
RASn*
PGn
input
output
output
1, 2, 4
—
1
1
0
1
CSn
PGn
PGn
output
input
output
0
—
0
—
—
0
1
0
PGn
PGn
PGn
input
output
input
output
0
—
0
1
0
PGn
PGn
PGn
input
output
input
7
1
1
Area n is in
Area n is in
normal space
DRAM*
space
1
0
1
CSn
PGn
PGn
input
output
n = 2 or 3
7
1
0
1
1
0
PGn
PGn
output
input
n =1 or 0
—
RASn*
output
1
CSn
output
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