Renesas H8S/2368 Series Hardware Manual page 182

Bit Bit Name
10 RTCK2
9 RTCK1
8 RTCK0
7 RFSHE
6 CBRM
5 RLW1
4 RLW0
Rev. 2.00, 05/03, page 130 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Refresh Counter Clock Select
These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0, the
refresh counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
Refresh Control
Refresh control can be performed. When
refresh control is not performed, the refresh
timer can be used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
CBR Refresh Control Mode
Selects CBR refreshing performed in parallel
with other external accesses, or execution of
CBR refreshing alone.
0: External access during CAS-before-RAS
refreshing is enabled
1: External access during CAS-before-RAS
refreshing is disabled
Refresh Cycle Wait Control
These bits select the number of wait states to
be inserted in a DRAM interface CAS-before-
RAS refresh cycle. This setting applies to all
areas designated as DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted