Renesas H8S/2368 Series Hardware Manual page 32

14.5.1 Multiprocessor Serial Data Transmission ............................................................ 552
14.5.2 Multiprocessor Serial Data Reception ................................................................. 554
14.6 Operation in Clocked Synchronous Mode ........................................................................ 558
14.6.1 Clock.................................................................................................................... 558
14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 559
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 560
14.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 563
14.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 565
14.7 Operation in Smart Card Interface Mode.......................................................................... 567
14.7.1 Pin Connection Example ..................................................................................... 567
14.7.2 Data Format (Except for Block Transfer Mode).................................................. 567
14.7.3 Block Transfer Mode ........................................................................................... 569
14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 569
14.7.5 Initialization ......................................................................................................... 570
14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 571
14.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 574
14.7.8 Clock Output Control........................................................................................... 575
14.8 IrDA Operation ................................................................................................................. 577
14.9 SCI Interrupts.................................................................................................................... 580
14.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 580
14.9.2 Interrupts in Smart Card Interface Mode ............................................................. 581
14.10 Usage Notes ...................................................................................................................... 583
14.10.1 Module Stop Mode Setting .................................................................................. 583
14.10.2 Break Detection and Processing .......................................................................... 583
14.10.3 Mark State and Break Sending ............................................................................ 583
14.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 583
14.10.5 Relation between Writes to TDR and the TDRE Flag ......................................... 584
14.10.6 Restrictions on Use of DMAC* or DTC.............................................................. 584
14.10.7 Operation in Case of Mode Transition................................................................. 584
2
Section 15 I C Bus Interface2 (IIC2) (Option) ..................................................589
15.1 Features............................................................................................................................. 589
15.2 Input/Output Pins .............................................................................................................. 591
15.3 Register Descriptions ........................................................................................................ 592
2
15.3.1 I C Bus Control Register A (ICCRA) .................................................................. 593
2
15.3.2 I C Bus Control Register B (ICCRB)................................................................... 594
2
15.3.3 I C Bus Mode Register (ICMR)........................................................................... 596
2
15.3.4 I C Bus Interrupt Enable Register (ICIER) .......................................................... 597
2
15.3.5 I C Bus Status Register (ICSR)............................................................................ 599
15.3.6 Slave Address Register (SAR)............................................................................. 601
2
15.3.7 I C Bus Transmit Data Register (ICDRT)............................................................ 601
Rev. 2.00, 05/03, page xxxii of lii