Renesas H8S/2368 Series Hardware Manual page 38

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2................................................................................... 100
Figure 5.5 Interrupt Exception Handling ................................................................................ 101
Figure 5.6 Contention between Interrupt Generation and Disabling....................................... 104
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller .......................................................................... 108
Figure 6.2 Read Strobe Negation Timing
(Example of 3-State Access Space) ....................................................................... 117
CS and Address Assertion Period Extension
Figure 6.3
(Example of 3-State Access Space and RDNn = 0) ............................................... 119
RAS Signal Assertion Timing
Figure 6.4
(2-State Column Address Output Cycle, Full Access)........................................... 127
Figure 6.5 Area Divisions ....................................................................................................... 133
CSn Signal Output Timing (n = 0 to 7).................................................................. 137
Figure 6.6
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space).......................... 138
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space) ........................ 139
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space.......................................................... 140
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space.......................................................... 141
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) ......... 142
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) .......... 143
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................... 144
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) ......... 145
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) .......... 146
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................... 147
Figure 6.17 Example of Wait State Insertion Timing ............................................................... 149
Figure 6.18 Example of Read Strobe Timing............................................................................ 150
Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended .................... 151
Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0) .......................................... 155
Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0) ............................................................................................................ 156
Example of Access Timing when RAS Signal Goes Low
Figure 6.22
from Beginning of T
Figure 6.23 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0).......................................................................................... 158
Figure 6.24 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) ..... 159
Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output)......... 161
Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output)......... 162
Figure 6.27 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ........ 163
Figure 6.28 Example of 2-CAS DRAM Connection................................................................. 164
Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0).............................. 165
Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1).............................. 166
Figure 6.31 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) ....... 167
Figure 6.32 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) ............ 168
Rev. 2.00, 05/03, page xxxviii of lii
State (CAST = 0) ................................................................ 157
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