Port A Data Direction Register (Paddr) - Renesas H8S/2368 Series Hardware Manual

9.8.1

Port A Data Direction Register (PADDR)

The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit Bit Name Initial Value
7 PA7DDR 0
6 PA6DDR 0
5 PA5DDR 0
4 PA4DDR 0
3 PA3DDR 0
2 PA2DDR 0
1 PA1DDR 0
0 PA0DDR 0
R/W Description
•
W
Modes 1 and 2
Pins PA4 to PA0 are address outputs.
W
For pins PA6 and PA5, when the corresponding
W
A22E and A21E bits are set to 1, setting a PADDR bit
W
to 1 makes the corresponding port A pin an address
W
output, while clearing the bit to 0 makes the pin an
input port. Clearing A22E and A21E bits to 0 makes
W
the corresponding port A pin an I/O port, and its
W
function can be switched with PADDR. For pin PA7,
when the A23E bit is set to 1, setting the PA7DDR bit
W
to 1 makes the pin an address output, while clearing
the bit to 0 makes the pin an input port. When the
CS7E bit is set to 1 while the A23E bit is cleared to 0,
pin PA7 functions as the CS7 output pin when
PA7DDR is set to 1, and as an input port when the bit
is cleared to 0. When the CS7E bit is cleared to 0, pin
PA7 is an I/O port, and its function can be switched
with PA7DDR.
•
Modes 4 and 7 (when EXPE = 1)
For pins PA6 to PA0, when the corresponding A22E
to A16E bits are set to 1, setting a PADDR bit to 1
makes the corresponding port A pin an address
output, while clearing the bit to 0 makes the pin an
input port. Clearing A22E to A21E bits to 0 makes the
corresponding port A pin an I/O port, and its function
can be switched with PADDR. For pin PA7, when the
A23E bit is set to 1, setting the PA7DDR bit to 1
makes the pin an address output, while clearing the
bit to 0 makes the pin an input port. When the CS7E
bit is set to 1 while the A23E bit is cleared to 0, pin
PA7 functions as the CS7 output pin when PA7DDR
is set to 1, and as an input port when the bit is
cleared to 0. When the CS7E bit is cleared to 0, pin
PA7 is an I/O port, and its function can be switched
with PA7DDR.
•
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev. 2.00, 05/03, page 341 of 820