C Bus Interrupt Enable Register (Icier) - Renesas H8S/2368 Series Hardware Manual

Bit Bit Name Initial Value R/W
2 BC2 0
1 BC1 0
0 BC0 0
2
15.3.4 I

C Bus Interrupt Enable Register (ICIER)

ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit Bit Name Initial Value R/W
7 TIE 0
6 TEIE 0
Description
R/W Bit Counter 2 to 0
R/W These bits specify the number of bits to be transferred next.
When read, the remaining number of transfer bits is
R/W
indicated. The data is transferred with one addition
acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to
BC0 are set to a value other than 000, the setting should
be made while the SCL line is low. The value returns to 000
at the end of a data transfer, including the acknowledge bit.
With the clock synchronous serial format, these bits should
not be modified.
000: 9
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
Description
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI)
at the rising of the ninth clock while the TDRE bit in ICSR is
1. TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Rev. 2.00, 05/03, page 597 of 820