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19.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
19.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or
standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a
reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation
stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the
RES pulse width specified in the AC Characteristics section.
19.9.2
Software Protection
Protection can be implemented against programming/erasing of all flash memory blocks by
clearing the SWE bit in FLMCR1 to 0 or setting the RAMS bit in the RAM emulation register
(RAMER) to 1 (emulation protection) by software (these operations must be executed in the on-
chip RAM or external memory). When protection is in effect, setting the P or E bit in FLMCR1
does not cause a transition to program mode or erase mode. By setting the erase block register 1
(EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks.
When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
19.9.3
Error Protection
In error protection, an error is detected when the CPU's runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• When an exception handling (excluding a reset) is started during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU releases the bus during programming/erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode
Rev. 2.00, 05/03, page 668 of 820
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