Figure 7.1 Block Diagram Of Dmac - Renesas H8S/2368 Series Hardware Manual

A block diagram of the DMAC is shown in figure 7.1.
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
Interrupt signals
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
Legend
DMAWER : DMA write enable register
DMATCR : DMA terminal control register
DMABCR : DMA band control register (for all channels)
DMACR : DMA control register
MAR : Memory address register
IOAR : I/O address register
ETCR : Execute transfer count register
Rev. 2.00, 05/03, page 200 of 820
Internal address bus
Control logic
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer

Figure 7.1 Block Diagram of DMAC

Address buffer
Processor
MAR_0AH
MAR_0BH
MAR_1AH
MAR_1BH
Internal data bus
MAR_0AL
IOAR_0A
ETCR_0A
MAR_0BL
IOAR_0B
ETCR_0B
MAR_1AL
IOAR_1A
ETCR_1A
MAR_1BL
IOAR_1B
ETCR_1B