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Notes:
*1 Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and
16 bits otherwise.
*2 For short address mode
*3 For full address mode
*4 For normal mode
*5 For smart card interface mode
*6 If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting,
the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for
group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for
group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
*7 Not supported by the H8S/2366.
Rev. 2.00, 05/03, page 722 of 820
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