Renesas H8S/2368 Series Hardware Manual page 49

Table 10.13 TIORL_0................................................................................................................389
Table 10.14 TIOR_1 ..................................................................................................................390
Table 10.15 TIOR_2 ..................................................................................................................391
Table 10.16 TIORH_3 ...............................................................................................................392
Table 10.17 TIORL_3................................................................................................................393
Table 10.18 TIOR_4 ..................................................................................................................394
Table 10.19 TIOR_5 ..................................................................................................................395
Table 10.20 TIORH_0 ...............................................................................................................396
Table 10.21 TIORL_0................................................................................................................397
Table 10.22 TIOR_1 ..................................................................................................................398
Table 10.23 TIOR_2 ..................................................................................................................399
Table 10.24 TIORH_3 ...............................................................................................................400
Table 10.25 TIORL_3................................................................................................................401
Table 10.26 TIOR_4 ..................................................................................................................402
Table 10.27 TIOR_5 ..................................................................................................................403
Table 10.28 Register Combinations in Buffer Operation...........................................................418
Table 10.29 Cascaded Combinations.........................................................................................422
Table 10.30 PWM Output Registers and Output Pins ...............................................................425
Table 10.31 Clock Input Pins in Phase Counting Mode ............................................................429
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1.......................................430
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2.......................................431
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3......................................432
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4.......................................433
Table 10.36 TPU Interrupts .......................................................................................................436
Section 11 Programmable Pulse Generator (PPG)
Table 11.1 Pin Configuration...................................................................................................455
Section 12 8-Bit Timers (TMR)
Table 12.1 Pin Configuration...................................................................................................475
Table 12.2 Clock Input to TCNT and Count Condition...........................................................478
Table 12.3 8-Bit Timer Interrupt Sources ................................................................................487
Table 12.4 Timer Output Priorities ..........................................................................................490
Table 12.5 Switching of Internal Clock and TCNT Operation ................................................492
Section 13 Watchdog Timer
Table 13.1 Pin Configuration...................................................................................................496
Table 13.2 WDT Interrupt Source ...........................................................................................502
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.1 Pin Configuration...................................................................................................509
Table 14.2 Relationships between N Setting in BRR and Bit Rate B......................................528
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)..................................529
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ...........................531
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................532
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)......................533
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .....534
Rev. 2.00, 05/03, page xlix of lii