Dma Band Control Registers H And L (Dmabcrh And Dmabcrl) - Renesas H8S/2368 Series Hardware Manual

Bit Bit Name
3 DTF3
2 DTF2
1 DTF1
0 DTF0
Legend
x: Don't care
7.3.5

DMA Band Control Registers H and L (DMABCRH and DMABCRL)

DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR
registers differ according to the transfer mode.
Short Address Mode:
• DMABCRH
Bit Bit Name
15 FAE1
14 FAE0
13 SAE1
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
Description
The same factor can be selected for more than
one channel. In this case, activation starts with
the highest-priority channel according to the
relative channel priorities. For relative channel
priorities, see section 7.5.12, Multi-Channel
Operation.
Description
Full Address Enable 1
Specifies whether channel 1 is to be used in
short address mode or full address mode. In
short address mode, channels 1A and 1B can
be used as independent channels.
0: Short address mode
1: Full address mode
Full Address Enable 0
Specifies whether channel 0 is to be used in
short address mode or full address mode. In
short address mode, channels 0A and 0B can
be used as independent channels.
0: Short address mode
1: Full address mode
Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
Rev. 2.00, 05/03, page 211 of 820