Figure 6.23 Example Of Timing With One Row Address Output Maintenance State (Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.23 shows an example of the timing when one T
Address bus
(
,
( )
Read
( )
Data bus
( )
Write
( )
Data bus
Note: n = 2, 3
Figure 6.23 Example of Timing with One Row Address Output Maintenance State
Rev. 2.00, 05/03, page 158 of 820
cycle, in which the RAS signal goes low, and the T
r
T
p
Row address
)
(RAST = 0, CAST = 0)
states, in which row address output is maintained,
rw
T T
r rw
cycle, in which
c1
state is set.
rw
T T
c1 c2
Column address
High
High