Figure 6.52 Example Of Idle Cycle Operation After Dram Access (Write After Read) (Idlc = 0, Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

DRAM space read External address space write DRAM space read
T T T T T T T T T T
p r c1 c2 i 1 2 3 c1 c2
Address bus
,
,
Data bus
Idle cycle
Figure 6.52 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
Rev. 2.00, 05/03, page 185 of 820