Block Transfer Mode; Figure 8.7 Memory Mapping In Repeat Mode; Table 8.6 Register Function In Block Transfer Mode - Renesas H8S/2368 Series Hardware Manual

SAR
or
DAR
8.5.3

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 8.6 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 8.6 Register Function in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Rev. 2.00, 05/03, page 288 of 820
Repeat area

Figure 8.7 Memory Mapping in Repeat Mode

Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Transfer
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Designates transfer count
DAR
or
SAR