Operation; Figure 11.2 Overview Diagram Of Ppg - Renesas H8S/2368 Series Hardware Manual

11.4

Operation

Figure 11.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
Pulse output pin
DDR
Normal output/inverted output

Figure 11.2 Overview Diagram of PPG

NDER
Q
Output trigger signal
C
Q PODR D Q NDR
Rev. 2.00, 05/03, page 463 of 820
D Internal data bus