Figure 6.47 Relationship Between Chip Select (Cs) And Read (Rd); Figure 6.48 Example Of Dram Full Access After External Read (Cast = 0) - Renesas H8S/2368 Series Hardware Manual

Address bus
(area A)
(area B)
Overlap period between
and
(a) No idle cycle insertion
Figure 6.47 Relationship between Chip Select (CS
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a T
timing in this case is shown in figure 6.48.
Note: The DRAM interface is not supported by the H8S/2366.
Address bus
Data bus
Figure 6.48 Example of DRAM Full Access after External Read
Rev. 2.00, 05/03, page 182 of 820
Bus cycle A Bus cycle B
T T T T T
1 2 3 1 2
(area B)
may occur
(ICIS1 = 0)
External read
T T
1
Bus cycle A
T
1
Address bus
(area A)
(area B)
(b) Idle cycle insertion
cycle is inserted, and a T
p
DRAM space read
T T T
2 3 p r
(CAST = 0)
Bus cycle B
T T T T
2 3 i 1
Idle cycle
(ICIS1 = 1, initial value)
CS) and Read (RD RD)
CS CS RD RD
cycle is not. The
i
T T
c1 c2
T
2