Figure 15.15 Sample Flowchart For Master Receive Mode - Renesas H8S/2368 Series Hardware Manual

16-bit single-chip microcomputer
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Mater receive mode
Clear TEND in ICSR
Set TRS = 0 (ICCRA)
Clear TDRE of ICSR
Set ACKBT = 0 (ICIER)
Dummy read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Yes
(Last receive
- 1)?
No
Read ICDRR
Set ACKBT = 1 (ICIER)
Set RCVD - 1 (ICCRA)
Read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP of ICSR
Write BBSY = 0
and SCP = 0
Read STOP of ICSR
No
STOP=1 ?
Yes
Read ICDRR
Set RCVD = 0 (ICCRA)
Set MST = 0 (ICCRA)
End

Figure 15.15 Sample Flowchart for Master Receive Mode

[1]
Clear TEND, select master receive mode, and then clear TDRE.
[2]
Set acknowledge to the transmitting device.
[1]
[3]
Dummy read ICDDR
[4]
Wait for 1 byte to be received.
[2]
[5]
Check if (last receive - 1)
[3]
[6]
Read the receive data, and clear RDRF to 0.
[7]
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
[4]
[8]
Read receive data of (final byte - 1), and clear RDRF to 0.
[9]
Wait for the final byte to be received.
[5]
[10] Clear STOP flag.
[6]
[11] Stop condition issuance
[12] Wait for the creation of stop condition.
[13] Read the receive data of the final byte, and clear RDRF to 0.
[7]
[14] Clear RCVD to 0.
[15] Set slave receive mode.
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Rev. 2.00, 05/03, page 613 of 820

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