Port F Data Direction Register (Pfddr) - Renesas H8S/2368 Series Hardware Manual

9.13.1

Port F Data Direction Register (PFDDR)

The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit Bit Name Initial Value
7 PF7DDR 1/0*
6 PF6DDR 0
5 PF5DDR 0
4 PF4DDR 0
3 PF3DDR 0
2 PF2DDR 0
1 PF1DDR 0
0 PF0DDR 0
Notes: *1 PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in mode 7.
*2 Not supported by the H8S/2366.
R/W Description
1 •
W
Pin PF7 functions as the φ output pin when the
W
corresponding PFDDR bit is set to 1, and as an input
W
port when the bit is cleared to 0.
W
Pin PF6 functions as the AS output pin when ASOE is
set to 1. When ASOE is cleared to 0, pin PF6 is an
W
I/O port and its function can be switched with
W
PF6DDR.
W
Pins PF5 and PF4 are automatically designated as
bus control outputs (RD and HWR).
W
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to 0, pin
PF3 is an I/O port and its function can be switched
with PF3DDR.
Pins PF2 and PF1 function as bus control output pins
(LCAS*
controller settings are made. When the CS output
enable bits (CS6E and CS5E) are set to 1, they
function as CS outputs. When the CS output enable
bits (CS6E and CS5E) are cleared to 0, pins PF2 and
PF1 are I/O ports and their functions can be switched
with the corresponding PFDDR bits.
Pin PF0 functions as a bus control input pin (WAIT)
when the appropriate bus controller settings are
made. Otherwise, this pin is an output port when the
corresponding PFDDR bit is set to 1, and an input
port when the bit is cleared to 0.
•
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input
port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions can
be switched with PFDDR.
Modes 1, 2, 4, and 7 (when EXPE = 1)
and UCAS*
2 2
) when the appropriate bus
Mode 7 (when EXPE = 0)
Rev. 2.00, 05/03, page 363 of 820