Table of Contents
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Type
Symbol
LCAS*
Bus control
RAS2*
RAS3*
WAIT*
OE*
(OE)*
Interrupt
NMI
signals
IRQ7 to
IRQ0
(IRQ7) to
(IRQ0)
DREQ1*
DMA controller
DREQ0*
(DMAC)*
TEND1*,
TEND0*
DACK1*,
DACK0*
16-bit timer
TCLKD
pulse unit
TCLKC
(TPU)
TCLKB
TCLKA
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
Rev. 2.00, 05/03, page 16 of 820
Pin No.
TFP-120
QFP-128
71
79
91
101
92
102
69
77
69,
77,
113
123
32
38
29 to 26,
33 to 30,
112 to 109,
122 to 119,
102 to 95
112 to 105
35,
41,
34
40
37,
43,
36
42
39,
45,
38
44
41,
47,
39,
45,
37,
43,
36
42
34,
40,
35,
41,
36,
42,
37
43
38,
44,
39
45
I/O
Function
Output Lower column address strobe signal
for accessing the 16-bit DRAM
space.
Output Row address strobe signal for the
DRAM interface.
Input
Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
Output Output enable signal for accessing
the DRAM space.
The output pins of OE and (OE) are
selected by the port function control
register 2 (PFCR2) of port 3.
Input
Nonmaskable interrupt request pin.
Fix high when not used.
Input
These pins request a maskable
interrupt.
The input pins of IRQn and (IRQn)
are selected by the IRQ pin select
register (ITSR) of the interrupt
controller. (n = 0 to 7)
Input
These signals request DMAC
activation.
Output These signals indicate the end of
DMAC data transfer.
Output DMAC single address transfer
acknowledge signals.
Input
External clock input pins for the timer.
Input/
TGRA_0 to TGRD_0 input capture
output
input/output compare output/PWM
output pins.
Input/
TGRA_1 and TGRB_1 input capture
output
input/output compare output/PWM
output pins.
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