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Register States In Each Operating Mode - Renesas H8S/2368 Series Hardware Manual

16-bit single-chip microcomputer

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23.3

Register States in Each Operating Mode

Register

Name

Reset

MRA

Initialized

SAR

Initialized

MRB

Initialized

DAR

Initialized

CRA

Initialized

CRB

Initialized

ICCRA_0

Initialized

ICCRB_0

Initialized

ICMR_0

Initialized

ICIER_0

Initialized

ICSR_0

Initialized

SAR_0

Initialized

ICDRT_0

Initialized

ICDRR_0

Initialized

ICCRA_1

Initialized

ICCRB_1

Initialized

ICMR_1

Initialized

ICIER_1

Initialized

ICSR_1

Initialized

SAR_1

Initialized

ICDRT_1

Initialized

ICDRR_1

Initialized

SEMR_2

Initialized

IPRA

Initialized

IPRB

Initialized

IPRC

Initialized

IPRD

Initialized

High-

Clock

Speed

Division Sleep

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Module

All Module

Software

Stop

Clock Stop

Standby

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Rev. 2.00, 05/03, page 723 of 820

Hardware

Standby

Module

Initialized

DTC

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

IIC2_0

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

IIC2_1

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

Initialized

SCI2

Initialized

INT

Initialized

Initialized

Initialized

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H8s series H8s/2300 series