Renesas H8S/2368 Series Hardware Manual page 24

6.5.3 Basic Timing........................................................................................................ 140
6.5.4 Wait Control ........................................................................................................ 148
6.5.5 Read Strobe (RD) Timing.................................................................................... 149
6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 150
6.6 DRAM Interface ............................................................................................................... 152
6.6.1 Setting DRAM Space........................................................................................... 152
6.6.2 Address Multiplexing .......................................................................................... 152
6.6.3 Data Bus............................................................................................................... 153
6.6.4 Pins Used for DRAM Interface............................................................................ 154
6.6.5 Basic Timing........................................................................................................ 155
6.6.6 Column Address Output Cycle Control ............................................................... 156
6.6.7 Row Address Output State Control...................................................................... 156
6.6.8 Precharge State Control ....................................................................................... 159
6.6.9 Wait Control ........................................................................................................ 160
6.6.10 Byte Access Control ............................................................................................ 163
6.6.11 Burst Operation.................................................................................................... 164
6.6.12 Refresh Control.................................................................................................... 168
6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 173
6.7 Burst ROM Interface......................................................................................................... 176
6.7.1 Basic Timing........................................................................................................ 176
6.7.2 Wait Control ........................................................................................................ 178
6.7.3 Write Access ........................................................................................................ 178
6.8 Idle Cycle.......................................................................................................................... 179
6.8.1 Operation ............................................................................................................. 179
6.8.2 Pin States in Idle Cycle ........................................................................................ 189
6.9 Write Data Buffer Function .............................................................................................. 189
6.10 Bus Release....................................................................................................................... 190
6.10.1 Operation ............................................................................................................. 190
6.10.2 Pin States in External Bus Released State............................................................ 192
6.10.3 Transition Timing ................................................................................................ 193
6.11 Bus Arbitration ................................................................................................................. 194
6.11.1 Operation ............................................................................................................. 194
6.11.2 Bus Transfer Timing............................................................................................ 195
6.12 Bus Controller Operation in Reset .................................................................................... 196
6.13 Usage Notes ...................................................................................................................... 196
6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 196
6.13.2 External Bus Release Function and Software Standby ........................................ 196
6.13.3 External Bus Release Function and CBR Refreshing .......................................... 196
6.13.4 BREQO Output Timing ....................................................................................... 197
Section 7 DMA Controller (DMAC).................................................................199
7.1 Features............................................................................................................................. 199
7.2 Input/Output Pins .............................................................................................................. 201
Rev. 2.00, 05/03, page xxiv of lii