Renesas H8S/2368 Series Hardware Manual page 44

Figure 14.30 Example of Reception Processing Flow ................................................................ 575
Figure 14.31 Timing for Fixing Clock Output Level .................................................................. 575
Figure 14.32 Clock Halt and Restart Procedure.......................................................................... 576
Figure 14.33 Block Diagram of IrDA ......................................................................................... 577
Figure 14.34 IrDA Transmit/Receive Operations ....................................................................... 578
Figure 14.35 Example of Synchronous Transmission Using DTC ............................................. 584
Figure 14.36 Sample Flowchart for Mode Transition during Transmission ............................... 586
Figure 14.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission) ...................................................... 587
Figure 14.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission)......................................................... 587
Figure 14.39 Sample Flowchart for Mode Transition during Reception..................................... 588
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Section 15 I C Bus Interface2 (IIC2) (Option)
Figure 15.1 Block Diagram of I
Figure 15.2 External Circuit Connections of I/O Pins............................................................... 591
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Figure 15.3 I C Bus Formats..................................................................................................... 602
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Figure 15.4 I C Bus Timing ...................................................................................................... 602
Figure 15.5 Master Transmit Mode Operation Timing 1 .......................................................... 604
Figure 15.6 Master Transmit Mode Operation Timing 2 .......................................................... 604
Figure 15.7 Master Receive Mode Operation Timing 1............................................................ 606
Figure 15.8 Master Receive Mode Operation Timing 2............................................................ 606
Figure 15.9 Slave Transmit Mode Operation Timing 1 ............................................................ 608
Figure 15.10 Slave Transmit Mode Operation Timing 2 ............................................................ 609
Figure 15.11 Slave Receive Mode Operation Timing 1.............................................................. 610
Figure 15.12 Slave Receive Mode Operation Timing 2.............................................................. 610
Figure 15.13 Block Diagram of Noise Canceler ......................................................................... 611
Figure 15.14 Sample Flowchart for Master Transmit Mode ....................................................... 612
Figure 15.15 Sample Flowchart for Master Receive Mode......................................................... 613
Figure 15.16 Sample Flowchart for Slave Transmit Mode ......................................................... 614
Figure 15.17 Sample Flowchart for Slave Receive Mode........................................................... 615
Figure 15.18 Timing of the Bit Synchronous Circuit.................................................................. 616
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter.......................................................................... 620
Figure 16.2 A/D Conversion Timing ........................................................................................ 627
Figure 16.3 External Trigger Input Timing............................................................................... 629
Figure 16.4 A/D Conversion Precision Definitions .................................................................. 631
Figure 16.5 A/D Conversion Precision Definitions .................................................................. 631
Figure 16.6 Example of Analog Input Circuit........................................................................... 632
Figure 16.7 Example of Analog Input Protection Circuit ......................................................... 634
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter.......................................................................... 638
Figure 17.2 Example of D/A Converter Operation ................................................................... 642
Section 19 Flash Memory (F-ZTAT Version)
Rev. 2.00, 05/03, page xliv of lii
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C Bus Interface2 .................................................................... 590