Change Of Irq Pin Select Register (Itsr) Setting; Note On Irq Status Register (Isr) - Renesas H8S/2368 Series Hardware Manual

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W
MOV.W
BNE
5.7.5

Change of IRQ Pin Select Register (ITSR) Setting

When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 7) of ISR
may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 7) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.
5.7.6

Note on IRQ Status Register (ISR)

Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from
ISR after a reset and then write 0 to clear the IRQnF flags.
R4,R4
L1
Rev. 2.00, 05/03, page 105 of 820